Tool was developed for the flow and is available alongside the old implementation. A database approach would enable easy modifications, big and small, and the database is constructed in such a way that IP-XACT can be regenerated from it. A database is planned to be used as an intermediate format between IP-XACT and VHDL. This thesis describes the update to the IP-XACT to VHDL flow. The previously developed tool that does the conversion has become very fragile to changes and its’ programming language differs from the rest of the flow. This IP-XACT file is interpreted and VHDL is generated based on its’ data. In this thesis project there is an existing register generator tool flow that uses IP-XACT as intermediate file format. Register bank generation tools enable developers to quickly generate registers for a SoC module according to a register configuration file. Register banks are fast memory of SoC modules and each SoC module requires their own set of registers to suit module’s needs. Automation tools do repetitive tasks and one of these tasks would be generation of register banks. ![]() ![]() Tools are used for design, automation and verification purposes. The System on Chip (SoC) field relies on tools and processes.
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